In a communications system, when a data signal is transmitted from a transmitter to a receiver, errors may be introduced into the data signal at several stages. In particular, there are three main stages which can be considered, these being the transmission channel (wired or wireless) between the transmitter and the receiver, the analogue circuitry of the receiver, and the digital circuitry of the receiver. For example, the transmission channel, which may be wired or wireless, may introduce noise or distortion (such as multipath distortion resulting from the interference of multiple reflections of the transmitted signal) into the data signal due to noise sources and interference, transmission medium irregularities, and attenuation of the data signal. Furthermore, the analogue circuitry of the receiver, which will typically perform functions such as analogue signal amplification, frequency conversion and analogue to digital conversion, may also introduce noise into the data signal. In either case these effects result in a loss of some of the data carried in the data signal. The digital circuitry on the other hand is typically considered to operate correctly, and is assumed not to introduce errors into a received digital signal.
Communications protocols commonly employ mechanisms such as Automatic Repeat reQuest (ARQ), Hybrid ARQ (HARQ), Forward Error Correction (FEC), the addition of explicit integrity checks such as Cyclic Redundancy Checks (CRCs) to permit estimates of correctness to be made by a data receiver, and interleaving to mitigate the effects of noise and the like in either the transmission medium, or the associated analogue circuitry. This renders the receiver tolerant to certain transmission or processing errors, either by correcting the result using redundant information, or by rejecting the result as being incorrect.
Iterative processing techniques for probability measurements of data bits being a one (1) or a zero (0) are described in “Iterative, Soft Signal Processing for Digital Communications” (Alek Kavcic, José M. F. Moura, Vijayakumar Bhagavatula; http://www.ece.cmu.edu/˜moura/papers/spm-jan04-kavcic-moura-kumar-ieeeexplore.pdf).
A self-timed architecture for low power digital signal processing is described in “Soft Digital Signal Processing Using Self-Timed Circuits” (Kuang, Yang) which uses self-timed circuits, which are robust at very low voltage, to allow the circuit to operate with a very low supply voltage, even if some data samples are missed due to this low voltage.
The Razor processor described in (WO-A-2004/084072) comprises error detection circuitry which detects digital processing errors and modifies the operating characteristics of the processor in dependence on a detected error rate.